In communications systems, a transmitter sends data streams to a receiver in symbols, such as bits of data. As the receiver clock is typically not synchronized with the transmitter clock, the receiver needs to correctly recover the clock from the received signal itself. In addition, when data is transmitted over a communication channel, it is usually distorted in terms of phase and amplitude due to various types of noise, such as fading, oscillator drift, frequency and phase offset, and receiver thermal noise. At the receiver, the system is also subject to noise and timing jitter in a time domain. Therefore, the receiver needs a timing recovery process to obtain symbol synchronization, particularly to correct the clock delay and derive the optimal clock phase that is used to sample the received signal and achieve the best Signal-to-Noise Ratio (SNR).
In some systems, a receiver is required to support multiple data rates, such as a full data rate (e.g., 50 Gbps) as well as a half (25 Gbps) and/or a quarter data rate (12.5 Gbps). Herein, the maximum data rate that the multi-rate receiver is capable of supporting is referred as the full rate, and a half rate refers to a data rate that is half of the full rate, etc. It is desirable that such a receiver can be implemented with minimal modifications from a receiver that only supports a single rate (or the full rate). FIG. 1 illustrates a data communication system 100 that includes a receiver capable of supporting multiple data rates in accordance with the prior art.
In a simplified form, the system 100 includes an optical transmitter 110, an optical fiber cable 140, an optical receiver 120 and an electrical receiver 130. Data of different transmission rates can propagate from the optical transmission 110 to the multi-rate electrical receiver 130. The optical transmitter includes a modulator to modulate data according to a modulation scheme, e.g., pulse-amplitude-modulation-4 (PAM-4). The modulated data is sent for transportation through the optical fiber cable 140. The optical receiver 120 operates to receive data from the optical fiber cable 140 and convert the received optical signal to an electrical signal via a photo detector (not shown). The electrical receiver 130 receives the signals from the optical receiver 120 and performs data and clock recovery.
The electrical receiver 130 includes an analog-to-digital converter (ADC) 131, a feed-forward equalizer (FFE) 134, a slicer 135, a timing recovery (TR) module 136 and a phase interpolator (PI) 137. The slicer 135 outputs the recovered and demodulated data based on appropriate constellation thresholds. Both the slicer input and the output are provided to the timing recovery (TR) module 136 for locating the correct sampling phase. The timing recovery module 136 may include a phase detector, a loop filter and a voltage controlled oscillator (VCO) (not shown). The timing recovery module 136 and the phase interpolator 137 in combination with the clock (CLK) feedback path to the ADC form a timing recovery loop.
To support a data rate that is only half and/or a quarter of the full rate, the electric receiver 130 additionally includes a low pass filter (LPF) 132 and a decimator 133 disposed upstream of the equalizer 134. The decimator 133 is configured to downsample the signal output from the LPF 132 by a factor of M, where M is 2 for the case of half rate and 4 for the case of quarter rate. For example, in response to receiving a signal transmitted in a half data rate, the ADC 131 operates in the same rate as in response to a full data rate signal. That is, regardless of the data rate being half of the full rate, the ADC is clocked by the full rate clock signal (CLK) output from the phase interpolator 137 and samples the analog signal in a full sampling rate. For example, for a time-interleaved multi-channel ADC, the full sampling rate can be multiple times of the clock rate. The sampled digital data is then supplied to the LPF 132.
The LPF 132 serves as an anti-aliasing filter that is necessary to remove high frequency noise resulting from the oversampling by the ADC. The LPF 132 can be implemented by using a half-band filter operable to reduce the bandwidth of the sampled data by a factor of 2. Another half-band filter can be added to reduce the bandwidth by a factor of 4. The decimator 133 operates to downsample the LPF output by dropping every second sample (M=2) for the case of half rate, and by dropping 3 for every 4 samples (M=4) for the case of quarter rate.
The FFE 134 receives the decimated signal and operates as a T-spaced equalizer (EQ), where T denotes the nominal symbol period as received at the electrical receiver 130. The equalized signal is then supplied to the slicer 135 to generate the demodulated and recovered data. In parallel, the equalized signal is supplied to the timing recovery module 136 and further to the phase interpolator 137 to generate the recovered clock (CLK) which is fed back to the ADC 131 as well as the downstream circuits that use the recovered clock.
The main drawback of this design is the additional hardware required for implementation of the LPF and the extra latency that the LPF adds to the timing recovery loop. The performance of timing recovery is negatively and significantly impacted as the loop latency becomes high relative to the timing recovery loop bandwidth due to the LPF latency.